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Integrated Circuit Systems, Inc.
ICS8304-01
LOW SKEW, 1-TO-4 LVCMOS / LVTTL INVERTING FANOUT BUFFER
FEATURES
* 4 LVCMOS / LVTTL outputs * LVCMOS/LVTTL clock input * Maximum output frequency: 166MHz * Output skew: 50ps (maximum) * Part-to-part skew: 600ps (maximum) * Small 8 lead SOIC package saves board space * 3.3V input, outputs may be either 3.3V or 2.5V supply modes * 0C to 70C ambient operating temperature * Lead-Free package fully RoHS compliant
GENERAL DESCRIPTION
The ICS8304-01 is a low skew, 1-to-4 Inverting Fanout B u f fe r a n d a m e m b e r o f t h e HiPerClockSTM HiPerClock S TM family of High Perfor mance Clock Solutions from ICS. The ICS8304-01 is characterized at full 3.3V for input VDD, and mixed 3.3V and 2.5V for output operating supply modes (VDDO). Guaranteed output and par t-to-par t skew characteristics make the ICS8304-01 ideal for those clock distribution applications demanding well defined perfor mance and repeatability.
ICS
BLOCK DIAGRAM
nQ0
PIN ASSIGNMENT
VDDO VDD CLK GND 1 2 3 4 8 7 6 5 nQ3 nQ2 nQ1 nQ0
nQ1 CLK nQ2
ICS8304-01
8-Lead SOIC 3.8mm x 4.8mm x 1.47mm package body M Package Top View
nQ3
8304AM-01
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REV. D MAY 23, 2005
Integrated Circuit Systems, Inc.
ICS8304-01
LOW SKEW, 1-TO-4 LVCMOS / LVTTL INVERTING FANOUT BUFFER
Type Power Power Input Power Output Output Output Output Description Output supply pin. Core supply pin. Pulldown LVCMOS / LVTTL clock input. Power supply ground. Inver ted version of clock input. LVCMOS / LVTTL interface levels. Inver ted version of clock input. LVCMOS / LVTTL interface levels. Inver ted version of clock input. LVCMOS / LVTTL interface levels. Inver ted version of clock input. LVCMOS / LVTTL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5 6 7 8 Name VDDO VDD CLK GN D nQ0 nQ1 nQ2 nQ3
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN CPD RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance (per output) Input Pulldown Resistor Output Impedance Test Conditions Minimum Typical 4 VDD, VDDO = 3.465V 51 7 15 Maximum Units pF pF k
8304AM-01
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REV. D MAY 23, 2005
Integrated Circuit Systems, Inc.
ICS8304-01
LOW SKEW, 1-TO-4 LVCMOS / LVTTL INVERTING FANOUT BUFFER
4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 112.7C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDDX Inputs, VDD Outputs, VDDO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Power Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 15 8 Units V V mA mA
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol VIH VIL IIH IIL VOH Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage; NOTE 1 VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V -5 2.6 0.5 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 1.3 150 Units V V A A V V
Output Low Voltage; NOTE 1 VOL NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information Section", "3.3V Output Load Test Circuit".
TABLE 4A. AC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol Parameter fMAX tPD Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise Time Output Fall Time 30% to 70% 30% to 70% 250 250 166MHz 2.3 Test Conditions Minimum Typical Maximum 166 3.5 50 600 500 500 60 Units MHz ns ps ps ps ps %
tsk(o) tsk(pp)
tR tF
odc Output Duty Cycle f 166MHz 40 All parameters measured at 166MHz unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. Measured from the rising edge of the input to the falling edge of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8304AM-01
www.icst.com/products/hiperclocks.html
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REV. D MAY 23, 2005
Integrated Circuit Systems, Inc.
ICS8304-01
LOW SKEW, 1-TO-4 LVCMOS / LVTTL INVERTING FANOUT BUFFER
Test Conditions Minimum 3.135 2.375 Typical 3.3 2.5 Maximum 3.465 2.625 15 8 Units V V mA mA
TABLE 3C. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current
TABLE 3D. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol VIH VIL IIH IIL VOH Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage; NOTE 1 VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V -5 2.1 0.5 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 1.3 150 Units V V A A V V
Output Low Voltage; NOTE 1 VOL NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information Section, "3.3V/2.5V Output Load Test Circuit".
TABLE 4B. AC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol Parameter fMAX tPD Maximum Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise Time Output Fall Time 30% to 70% 30% to 70% 250 250 166MHz 2.5 Test Conditions Minimum Typical Maximum 166 3.6 50 600 500 500 60 Units MHz ns ps ps ps ps %
tsk(o) tsk(pp)
tR tF
odc Output Duty Cycle f 166MHz 40 All parameters measured at 166MHz unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. Measured from the rising edge of the input to the falling edge of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8304AM-01
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REV. D MAY 23, 2005
Integrated Circuit Systems, Inc.
ICS8304-01
LOW SKEW, 1-TO-4 LVCMOS / LVTTL INVERTING FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V5% 2.05V5% 1.25V5%
VDD, VDDO
SCOPE
Qx
V DD VDDO
SCOPE
Qx
LVCMOS
GND
LVCMOS
GND
VDDO 2
VDDO 2
-1.65V5%
-1.25V5%
3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT
nQx
V
nQx
2
DDO
V
DDO
PART 1
2
V
nQy
DDO
V
DDO
2 tsk(o)
nQy PART 2
2 tsk(pp)
OUTPUT SKEW
PART-TO-PART SKEW
70% 30% tR
70%
CLK
VDD 2 VDDO 2
tPD
Clock Outputs
30% tF
nQ0:nQ3
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
nQ0:nQ3
V
DDO
t PW
t
PERIOD
2
OUTPUT DUTY CYLE/PULSE WIDTH/PERIOD
8304AM-01
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REV. D MAY 23, 2005
Integrated Circuit Systems, Inc.
ICS8304-01
LOW SKEW, 1-TO-4 LVCMOS / LVTTL INVERTING FANOUT BUFFER RELIABILITY INFORMATION
TABLE 5. JAVS. AIR FLOW TABLE
FOR
8 LEAD SOIC
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3C/W 112.7C/W
200
128.5C/W 103.3C/W
500
115.5C/W 97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8304-01 is: 416
8304AM-01
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REV. D MAY 23, 2005
Integrated Circuit Systems, Inc.
ICS8304-01
LOW SKEW, 1-TO-4 LVCMOS / LVTTL INVERTING FANOUT BUFFER
FOR
PACKAGE OUTLINE - SUFFIX M
8 LEAD SOIC
TABLE 6. PACKAGE DIMENSIONS - SUFFIX M
SYMBOL N A A1 B C D E e H h L 5.80 0.25 0.40 0 1.35 0.10 0.33 0.19 4.80 3.80 1.27 BASIC 6.20 0.50 1.27 8 Millimeters MINIMUN 8 1.75 0.25 0.51 0.25 5.00 4.00 MAXIMUM
Reference Document: JEDEC Publication 95, MS-012
8304AM-01
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REV. D MAY 23, 2005
Integrated Circuit Systems, Inc.
ICS8304-01
LOW SKEW, 1-TO-4 LVCMOS / LVTTL INVERTING FANOUT BUFFER
Marking 8304AM01 8304AM01 8304A01L 8304A01L Package 8 lead SOIC 8 lead SOIC 8 lead "Lead-Free" SOIC 8 lead "Lead-Free" SOIC Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 6. ORDERING INFORMATION
Part/Order Number ICS8304AM-01 ICS8304AM-01T ICS8304AM-01LF ICS8304AM-01LFT
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8304AM-01
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REV. D MAY 23, 2005
Integrated Circuit Systems, Inc.
ICS8304-01
LOW SKEW, 1-TO-4 LVCMOS / LVTTL INVERTING FANOUT BUFFER
REVISION HISTORY SHEET Description of Change AC Characteristics Table - revised tpLH row to tPD and revised NOTE 1. Deleted tpHL row. AC Characteristics Table - revised tpLH row to tPD and revised NOTE 1. Deleted tpHL row. Updated Figures. AC Characteristics Table - changed tsk(pp) Par t-to-Par t Skew from 250ps Max. to 600ps Max. 5/20/02 AC Characteristics Table - changed tsk(pp) Par t-to-Par t Skew from 250ps Max. to 600ps Max. Ordering Information, updated marking from 8304-01 to 8304AM01 Pin Descripiton Table - revised VDD description to read "Core supply pin." (Also changed in Power Supply tables.) Deleted Pullup from note. Pin Characteristics Table -CIN changed 4pF max. to 4pF typical. Deleted RPULLUP row. Ordering Information Table - changed Par t/Order number ICS8304M-01/-01T to ICS8304AM-01/-01T. Updated format throughout data sheet. Features Section - added Lead-Free bullet. Ordering Information Table - add Lead-Free par ts. Date
Rev
Table 4A 4B
Page 3 4 6&7
B
4/9/02
4A C 4B C 6 T1 T2 D T6
3 4 10 2 2 10
6/17/02
3/1/04
D
T6
1 8
5/23/05
8304AM-01
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REV. D MAY 23, 2005

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